LTC2942I View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2942I' PDF : 16 Pages View PDF
LTC2942
APPLICATIONS INFORMATION
acknowledges and then the master sends a command
byte which indicates which internal register the master is
to read. The LTC2942 acknowledges and then latches the
command byte into its internal register address pointer. The
master then sends a repeated START condition followed
by the same seven bit address with the R/W bit now set
to one. The LTC2942 acknowledges and sends the con-
tents of the requested register. The transmission is ended
when the master sends a STOP condition. If the master
acknowledges the transmitted data byte, the LTC2942
increments its address pointer and sends the contents of
the following register as depicted in Figure 7.
Alert Response Protocol
In a system where several slaves share a common inter-
rupt line, the master can use the alert response address
(ARA) to determine which device initiated the interrupt
(Figure 8).
The master initiates the ARA procedure with a START con-
dition and the special 7-bit ARA bus address (0001100)
followed by the read bit (R) = 1. If the LTC2942 is asserting
the AL/CC pin in alert mode, it acknowledges and responds
by sending its 7-bit bus address (1100100) and a 1. While
it is sending its address, it monitors the SDA pin to see
if another device is sending an address at the same time
using standard I2C bus arbitration. If the LTC2942 is send-
ing a 1 and reads a 0 on the SDA pin on the rising edge of
SCL, it assumes another device with a lower address is
sending and the LTC2942 immediately aborts its transfer
and waits for the next ARA cycle to try again. If transfer
is successfully completed, the LTC2942 will stop pulling
down the AL/CC pin and will not respond to further ARA
requests until a new Alert event occurs.
PC Board Layout Suggestions
Keep all traces as short as possible to minimize noise and
inaccuracy. Use a 4-wire Kelvin sense connection for the
sense resistor, locating the LTC2942 close to the resistor
with short sense traces to the SENSE+ and SENSE– pins.
Use wider traces from the resistor to the battery, load
and/or charger (see Figure 11). Put the bypass capacitor
close to SENSE+ and GND.
TO
CHARGER/LOAD
RSENSE
TO BATTERY
1
6
C2
LTC2942
5
3
4
2942 F10
Figure 11. Kelvin Connection on Sense Resistor
S ALERT RESPONSE ADDRESS R A DEVICE ADDRESS A P
0001100
10
11001001
1
2942 F08
Figure 8. LTC2942 Serial Bus SDA Alert Response Protocol
S ADDRESS W A REGISTER A DATA P
10ms
S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P
1100100 0 0 01h 0 BC
1100100 0 0 08h 0 1100100 1 0 F1h 0 80h 1
2942 F09
Figure 9. Voltage Conversion Sequence
S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P
1100100 0 0 02h 0
1100100 1 0 80h 0 01h 1
2942 F10
Figure 10. Reading the LTC2942 Accumulated Charge Registers (C, D)
2942f
14
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