LTC3701 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC3701' PDF : 20 Pages View PDF
LTC3701
APPLICATIO S I FOR ATIO
error amplifier. The regulated output voltage is deter-
mined by:
VOUT = 0.8V • 1+ RR21
For most applications, an 80k resistor is suggested for R1.
To prevent stray pickup, a 100pF capacitor is suggested
across R1 close to the LTC3701.
105
VREF
100
95
MAXIMUM
OUTPUT CURRENT
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3701 F05
Figure 5. Line Regulation of VREF and Maximum Output Current
VOUT
1/2 LTC3701
VFB
R2
100pF R1
3701 F06
Figure 6. Setting Output Voltage
Phase-Locked Loop and Frequency Synchronization
The LTC3701 has a phase-locked loop comprised of an
internal voltage-controlled oscillator and phase detector.
This allows the turn-on of the external P-channel MOSFET
of controller 1 to be locked to the rising edge of an external
frequency source. The turn-on of controller 2’s external
P-channel MOSFET is thus 180 degrees out of phase to the
external clock. The nominal frequency range of the volt-
age-controlled oscillator is 280kHz to 775kHz. The phase
detector is an edge sensitive digital type that provides zero
degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false lock to harmonics of the external oscillator.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency is shown in Figure 7 and specified in the
electrical characteristics table. Note that the LTC3701 can
only be synchronized to an external clock whose fre-
quency is within the frequency range of the LTC3701’s
internal oscillator, which is specified in the electrical
characteristics table. A simplified block diagram of the
PLL is shown in Figure 8.
If the external frequency (VEXTCLK/MODE) is greater than
the internal oscillator frequency fOSC, current is sourced
continuously, pulling up the PLLLPF pin. When the exter-
nal frequency is less than fOSC, current is sunk continu-
ously, pulling down the PLLLPF pin. If the external and
internal frequencies are the same but exhibit a phase dif-
ference, the current sources turn on for an amount of time
corresponding to the phase difference. The voltage on the
PLLLPF pin is adjusted until the phase and frequency of
the external oscillators are identical. At the stable operat-
ing point, the phase comparator output is high impedance
and the filter capacitor CLP holds the voltage.
The loop filter components CLP and RLP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components RLP and CLP determine how fast the loop
acquires lock. Typically, RLP = 10k and CLP is 2200pF to
0.01µF. When not synchronized to an external clock, the
800
750
700
650
600
550
500
450
400
350
300
250
0
0.4 0.8 1.2 1.6 2.0 2.4
PLLLPF PIN VOLTAGE (V)
3701 F07
Figure 7. Relationship Between Oscillator Frequency
and Voltage at PLLLPF Pin
3701fa
13
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