LTC3701 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC3701' PDF : 20 Pages View PDF
LTC3701
APPLICATIO S I FOR ATIO
internal oscillator frequency may be set by applying a DC
voltage to the PLLLPF pin. 550kHz operation can be
selected by floating the PLLLPF pin. The PLLLPF pin may
be connected to voltages as high as VIN.
EXTERNAL
OSCILLATOR
EXTCLK/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
RLP
CLP
PLLLPF
10k
OSCILLATOR
3701 F08
Figure 8. Phase-Locked Loop Block Diagram
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3701 circuits: 1) LTC3701 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, 4) voltage
drop of the output diode and 5) transition losses.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, that excludes MOSFET
driver currents. VIN current results in a small loss that
increases with VIN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from PVIN to ground. The
resulting dQ/dt is a current out of PVIN, which is
14
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFET, inductor and sense resistor. In continuous
mode, the average output current flows through L but
is “chopped” between the P-channel MOSFET in series
with RSENSE and the output diode. The MOSFET RDS(ON)
plus RSENSE multiplied by duty cycle can be summed
with the resistance of L to obtain I2R losses.
4) The output diode is a major source of power loss at high
currents and is worse at high input voltages. The diode
loss is calculated by multiplying the forward voltage
times the load current times the diode duty cycle.
5) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2 (VIN)2IO(MAX)CRSS(f)
Other losses, including CIN and COUT ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
Foldback Current Limiting
As described in the Output Diode Selection, the worst-
case diode dissipation occurs with a short-circuited out-
put when the diode conducts the current limit value almost
continuously. To prevent excessive heating in the diode,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding di-
odes DFB1 and DFB2 between the output and the ITH/RUN
pin as shown in Figure 9. In a hard short (VOUT = 0V), the
current will be reduced to approximately 50% of the
maximum output current.
1/2 LTC3701
ITH/RUN VFB
R2 +
R1
VOUT
DFB1
DFB2
3701 F09
Figure 9. Foldback Current Limiting
3701fa
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