LTC3776 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3776
Linear Technology
'LTC3776' PDF : 28 Pages View PDF
LTC3776
U
OPERATIO (Refer to Functional Diagram)
output noise spectrum of a conventional buck switching
converter (1/2 of LTC3776 with spread spectrum opera-
tion disabled) with VIN = 5V, VOUT = 2.5V and IOUT = 2A.
Unlike conventional buck converters, the LTC3776’s inter-
nal oscillator can be selected to produce a clock pulse
whose frequency is randomly varied between 450kHz and
580kHz by tying the SYNC/SSEN pin to VIN. This has the
benefit of spreading the switching noise over a range of
frequencies, thus significantly reducing the peak noise.
Figures 1c and 1d show the output noise spectrum of the
LTC3776 (with spread spectrum operation enabled) with
VIN = 5V, VOUT = 2.5V and IOUT = 1A. Note the significant
reduction in peak output noise (>20dBm).
Dropout Operation
When the input supply voltage (VIN) decreases towards the
output voltage, the rate of change of the inductor current
while the external P-channel MOSFET is on (ON cycle)
decreases. This reduction means that the P-channel MOS-
FET will remain on for more than one oscillator cycle if the
inductor current has not ramped up to the threshold set by
the EAMP on the ITH pin. Further reduction in the input
supply voltage will eventually cause the P-channel MOS-
FET to be turned on 100%; i.e., DC. The output voltage will
then be determined by the input voltage minus the voltage
drop across the P-channel MOSFET and the inductor.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorporated
in the LTC3776. When the input supply voltage (VIN) drops
below 2.3V, the external P- and N-channel MOSFETs and
all internal circuitry are turned off except for the undervolt-
age block, which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When controller 1 is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE1+ and
SW1 pins) allowed across the external P-channel MOSFET
is determined by:
( ) ∆VSENSE(MAX)1
=
A1
VITH1 –
10
0.7V
12
where A1 is a constant determined by the state of the IPRG
pins. Floating the IPRG1 pin selects A1 = 1; tying IPRG to
VIN selects A1 = 5/3; tying IPRG1 to SGND selects A1 =
2/3. The maximum value of VITH1 is typically about 1.98V,
so the maximum sense voltage allowed across the exter-
nal P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG1 pin.
When controller 2 is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE2+ and
SW2 pins) allowed across the external P-channel MOSFET
is determined by:
( ) ∆VSENSE(MAX)
=
A2 VITH2 – 1.3V
4.6
,VITH2
≥ 1.3V
( ) ∆VSENSE(MAX)
=
A2 VITH2 – 1.3V
5.4
,VITH2
< 1.3V
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG2 pin selects A2 = 1; tying IPRG2
to VIN selects A = 5/3; tying IPRG2 to SGND selects A2 =
2/3. The maximum value of VITH2 is typically about 1.98V,
so the maximum sense voltage allowed across the exter-
nal P-channel MOSFET is 147mV, 100mV or 245mV for
the three respective states of the IPRG2 pin. The minimum
value of VITH2 is typically about 0.7V, so the minimum
(most negative) peak sense voltage is –112mV, –75mV or
–188mV, respectively.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 2.
110
100
90
80
70
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3776 F02
Figure 2. Maximum Peak Current vs Duty Cycle
3776f
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