LTC4099EUDC View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4099EUDC' PDF : 36 Pages View PDF
LTC4099
Operation
Table 5 lists the possible safety timer settings from 1 to 8
hours, and how to decode them. The default state for the
LTC4099 safety timer is 4 hours.
Table 5. Safety Timer Decode
SAFETY TIMER SETTINGS
TIMER2
TIMER1
TIMER0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
*Default Setting
TIMEOUT
4 Hours*
5 Hours
6 Hours
7 Hours
8 Hours
1 Hour
2 Hours
3 Hours
The DISABLE_CHARGER bit can be used to prevent battery
charging if needed. This bit should be used with caution
as it can prevent the battery charger from bringing up
the battery voltage. Without the ability to address the I2C
port, only a low voltage on DVCC will clear the I2C port to
its default state and re-enable charging.
The ENABLE_BATTERY_CONDITIONER bit enables the
automatic battery load circuit in the event of simultaneously
high battery voltage and temperature. See the Overtem-
perature Battery Conditioner section.
The VFLOAT = 4.2V bit controls the final float voltage of the
LTC4099’s battery charger. A 1 in this bit position changes
the charger from the default float voltage value of 4.100V
to the higher 4.200V level.
The TREG = 85°C control bit changes the LTC4099’s battery
charger junction thermal regulation temperature from its
default value of 105°C to a lower setting of 85°C. This may
be used to reduce heat in highly thermally compromised
systems. In general, the high efficiency charging system
of the LTC4099 will keep the junction temperature low
enough to avoid junction thermal regulation.
The third and final byte of input data at sub address 0x02
is the mask register. The mask register determines which
status change events or categories will be allowed to gener-
ate an interrupt. A 1 written to a given position in the mask
register allows status change in that category to generate
an interrupt. A zero in a given position in the mask register
24
prohibits the generation of an interrupt. The start-up state
of the LTC4099 is all zeros for this register indicating that
no interrupts will be generated without explicit request via
the I2C port. See the Interrupt Generation section.
Output Data
One status byte may be read from the LTC4099. Table 6
represents the status byte information. A 1 read back in
any of the bit positions indicates that the condition is true.
For example, 1s read back from bits 7 and 2 indicate that
power is available at VBUS, and that the battery charger’s
thermistor has halted charging due to an undertemperature
condition at the battery.
Table 6. LTC4099 Status Data Bytes
READ BYTE
STATUS REGISTER
Bit 7 (MSB)
USBGOOD
Bit 6
WALLGOOD
Bit 5
BADCELL
Bit 4
THERMAL REG
Bit 3
NTC1
See Table 7
Bit 2
NTC0
Bit 1
CHRGR1
See Table 8
Bit 0 (LSB)
CHRGR0
Bit 7 in the status byte indicates the presence of power
at VBUS. Criteria for determining this status bit is derived
from the undervoltage lockout circuit on VBUS and is given
by the electrical parameters VUVLO and VDUVLO.
Bit 6 indicates the presence of voltage available at the WALL
pin and is derived from the WALL undervoltage lockout
circuit. Like the VBUS pin, this pin has both an absolute
voltage detection level given by the electrical parameter
VWALL, as well as a level relative to BAT given by ∆VWALL.
Both of the conditions must be met for bit 6 to indicate
the presence of power at WALL.
Bit 5 indicates that the battery has been below the pre-
charge threshold level of approximately 2.85V for more
than one-half hour while the charger was attempting to
charge. When this occurs, it is usually the result of a de-
fective cell. However, in some cases a bad cell indication
may be caused by system load prioritization over battery
charging. System software can test for this by forcing a
reduction of system load and restarting the battery charger
4099fd
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