LTC4370IMSPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4370IMSPBF' PDF : 20 Pages View PDF
LTC4370
Applications Information
External CPO Supply
The internal charge pump takes milliseconds to charge
up the CPO capacitor especially during device power-up.
This time can be shortened by connecting an external
supply to the CPO pin. A series resistor is needed to limit
the current into the internal clamp between the CPO and
VIN pins. The CPO supply should also be higher than the
main input supply to meet the gate drive requirements
of the MOSFET. Figure 5 shows such a 3.3V load share
application, where a 12V supply is connected to the CPO
pins through a 1k resistor. The 1k limits the current into
the CPO pin when the VIN pin is grounded. For the 8.7V
of gate drive (12V – 3.3V), logic-level MOSFETs would be
an appropriate choice for M1 and M2.
Loop Stability
The servo amplifier loop is compensated by the gate
capacitance of the N-channel power MOSFET. No further
compensation components are normally required. In the
case when a MOSFET with less than 1nF gate capacitance
is chosen, a 1nF compensation capacitor connected across
the gate and source might be required.
The load sharing control loop is compensated by the
capacitor from the COMP pin to ground. This capacitor
should be at least 50× the input capacitance CISS of the
MOSFET. A larger capacitor improves stability at the ex-
pense of increased sharing closure delay, while a smaller
capacitor can cause the two supply currents to switch back
and forth before settling. The COMP capacitor can be just
10× CISS when a CPO capacitor is omitted, i.e., when fast
gate turn-on is not used (see Figure 6).
Input and Output Capacitance for Pulsed Loads
For pulsed loads, the load current will be shared every cycle
at frequencies below 100Hz. At higher frequencies, each
cycle’s current may not be shared but the time average of
the currents will be. Bypassing capacitance on the inputs
should be provided to minimize glitches and ripple. This
is important since the controller tries to compensate for
the supply voltage differences to achieve load sharing.
Sufficient load capacitance should also be provided to
enhance the DC component of the load current presented
to the load share circuit. It is also important to design
IL • RDS(ON) below 75mV, as mentioned earlier.
With very low duty cycle or very low frequency loads,
the COMP voltage will rail whenever the load current falls
below the sharing threshold of VEA(OS)/RS for hundreds of
milliseconds. At the start of the next load cycle there will
be a sharing closure delay as COMP slews to its operating
point around 0.7V or 1.24V. To avoid this delay, maintain
the load current above VEA(OS)/RS.
VINA
3.3V
1k
12V
1k
VINB
3.3V
M1
TO SENSE
C1
RESISTOR
39nF
VIN1
GATE1
CPO1
LTC4370
CPO2
VIN2
C2
39nF
GATE2
4370 F05
TO SENSE
M2
RESISTOR
VINA
12V
NC
M1
SUM85N03-06P
CVCC
0.1µF
R3
47.5k
EN1 CPO1
VCC
GND
RANGE
EN2 CPO2
VIN1 GATE1
OUT1
LTC4370
FETON1
FETON2
OUT2
VIN2 GATE2 COMP
NC
VINB
12V
M2
SUM85N03-06P
R4
2.7k
D1
R1
2.5mΩ OUT
R2
10A
2.5mΩ
CC
0.039µF
4370 F06
D1: RED LED, LN1251C
Figure 5. 3.3V Load Share with External 12V Supply
Powering CPO for Faster Start-Up and Refresh
Figure 6. Current Sharing 12V Supplies
4370f
13
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