LTC5587IDD View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5587IDD' PDF : 20 Pages View PDF
LTC5587
PIN FUNCTIONS
SDO (Pin 1): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
SCK (Pin 2): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions
on the falling edge of SCK.
OVDD (Pin 3): ADC Output Driver Supply Voltage, 1.0V
to 3.6V. OVDD should be bypassed with a 1μF ceramic
capacitor. OVDD can be driven separately from VDD and
OVDD can be higher than VDD.
VOUT (Pin 4): Detector Analog Voltage Output. An internal
series 300Ω resistor at the detector output allows for
simple R-C filtering with a capacitor placed on this pin to
GND. A 1000pF capacitor is recommended for a corner
frequency of 500kHz.
CSQ (Pin 6): Optional low-frequency range extension
capacitor for frequencies below 250MHz. Connect 0.01μF
from this pin to ground for 10MHz operation.
RF (Pin 7): RF Input Voltage. Should be externally
DC-blocked. A capacitor of 1000pF is recommended. This
pin has an internal 205Ω termination.
VCC (Pin 8): Detector Power Supply Voltage, 2.7V to 3.6V.
Can be connected to the VDD voltage supply. VCC should
be bypassed with a 1μF ceramic capacitor. If VCC and VDD
are tied together, then bypass with 2.2μF.
EN (Pin 9): Detector Enable. A logic low or no-connect
on the enable pin shuts down the detector. A logic high
enables the detector. An internal 500k pull-down resistor
ensures the detector is off when the pin is left floating.
VREF (Pin 10): ADC Reference Input Voltage. VREF defines
the input span of the ADC, 0V to VREF. The VREF range
is 1.4V to VDD. Bypass to ground with a 1μF ceramic
capacitor.
VDD (Pin 11): ADC Power Supply Voltage, 2.7V to 3.6V.
VDD should be bypassed with a 1μF ceramic capacitor.
CONV (Pin 12): Convert Input. This active high signal starts
a conversion on the rising edge. The ADC automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
GND (Pin 5, Exposed Pad Pin 13): Ground. For high-
frequency operation, backside ground connection should
have a low-inductance connection to the pcb ground using
many through-hole vias. See layout information.
BLOCK DIAGRAM
RF
7
13
EXPOSED
PAD
150kHz LPF
RMS
DETECTOR
OUTPUT
BUFFER
4
VOUT
300Ω
S/H
BIAS
6 CSQ
EN
9
8 VCC
GND
5
11
VDD
3
OVDD
12-BIT ADC
THREE-STATE
SERIAL OUTPUT
PORT
SDO
1
10 VREF
TIMING
LOGIC
SCK
2
CONV
12
5587 BD
5587f
10
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