LTC5599
Appendix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
–81
–96
31
001111111
–80
–64
0
001000000
–79
–64
1
001000001
–78
–64
2
001000010
–77
–64
3
001000011
–76
–64
4
001000100
–75
–64
5
001000101
–74
–64
6
001000110
–73
–64
7
001000111
–72
–64
8
001001000
–71
–64
9
001001001
–70
–64
10
001001010
–69
–64
11
001001011
–68
–64
12
001001100
–67
–64
13
001001101
–66
–64
14
001001110
–65
–64
15
001001111
–64
–64
16
001010000
–63
–64
17
001010001
–62
–64
18
001010010
–61
–64
19
001010011
–60
–64
20
001010100
–59
–64
21
001010101
–58
–64
22
001010110
–57
–64
23
001010111
–56
–64
24
001011000
–55
–64
25
001011001
–54
–64
26
001011010
–53
–64
27
001011011
–52
–64
28
001011100
–51
–64
29
001011101
–50
–64
30
001011110
–49
–64
31
001011111
–48
–32
0
000100000
–47
–32
1
000100001
–46
–32
2
000100010
–45
–32
3
000100011
–44
–32
4
000100100
–43
–32
5
000100101
–42
–32
6
000100110
–41
–32
7
000100111
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
–40
–32
8
000101000
–39
–32
9
000101001
–38
–32
10
000101010
–37
–32
11
000101011
–36
–32
12
000101100
–35
–32
13
000101101
–34
–32
14
000101110
–33
–32
15
000101111
–32
–32
16
000110000
–31
–32
17
000110001
–30
–32
18
000110010
–29
–32
19
000110011
–28
–32
20
000110100
–27
–32
21
000110101
–26
–32
22
000110110
–25
–32
23
000110111
–24
–32
24
000111000
–23
–32
25
000111001
–22
–32
26
000111010
–21
–32
27
000111011
–20
–32
28
000111100
–19
–32
29
000111101
–18
–32
30
000111110
–17
–32
31
000111111
–16
0
0
x00000000
–15
0
1
x00000001
–14
0
2
x00000010
–13
0
3
x00000011
–12
0
4
x00000100
–11
0
5
x00000101
–10
0
6
x00000110
–9
0
7
x00000111
–8
0
8
x00001000
–7
0
9
x00001001
–6
0
10
x00001010
–5
0
11
x00001011
–4
0
12
x00001100
–3
0
13
x00001101
–2
0
14
x00001110
–1
0
15
x00001111
0
0
16
x00010000
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