LTC5599
appendix
Table 11. Serial Port Register Bit Field Summary
BITS
FUNCTION
DESCRIPTION
VALID VALUES DEFAULT
AGCTRL
CHIPID[7:0]
Analog Gain Control Enable
Chip ID
Enables analog control through VCTRL (Pin 1) when AGCTRL = 1.
0, 1
1
1
1
CLO[3:0]
LO Port Match Cap Array
LO port match, automatically adjusted through programming FREQ[6:0]
0x00 to 0x0F 0x00
CLOO[3:0] LO Port Cap Array Override Programs LO port match capacitor array when CLOEN = 0
0x00 to 0x0F 0x00
CLOEN
Automatic LO Match Enable Automatic LO port impedance matching enabled when CLOEN = 1. Override
0, 1
1
bits CLOO[3:0] control LO port match when CLOEN = 0.
CPPM0[5:0] CppQ Fine Control
CppQ = CPPM0[5:0] + number of 1’s in CPPM1[6:0] × 64
0x00 to 0x5F 0xXX
CPPM1[6:0] CppQ Coarse Control
0x00 to 0x7F 0x0X
CPPP0[5:0] CppI Fine Control
CppI = CPPP0[5:0] + number of 1’s in CPPP1[6:0] × 64
0x00 to 0x5F 0xXX
CPPP1[6:0] CppI Coarse Control
0x00 to 0x7F 0x0X
FREQ[6:0] Poly-Phase Filter Frequency Programs the center frequency of the poly-phase filter, according to Table 5. 0x00 to 0x79 0x2E
FUSE[3:0]
Fuse Read Out
0x00 to 0x0F 0x0X
GAIN[4:0]
Coarse Digital Gain Control Programs the conversion gain in 1dB steps, according to Table 3.
0x00 to 0x13 0x04
GAINF[3:0] Fine Digital Gain Control
Conversion gain control in approximately 0.1dB steps, when TEMPCORR = 1. 0x00 to 0x0F 0x00
GMI0[6:0] Fine GMI DAC Read-Out
BBMI input stage gain GmI.
0x00 to 0x7F 0x08
GMI1[7:0] Coarse GMI DAC Read-Out1 GmI = GMI0[6:0] + (number of 1’s in GMI1[7:0] and GMI2[6:0]) × 128
0x00 to 0x07 0xFF
GMI2[6:0] Coarse GMI DAC Read-Out2
0x00 to 0x07 0x01
GMQ0[6:0] Fine GMQ DAC Read-Out
BBMQ input stage gain GmQ.
0x00 to 0x7F 0x08
GMQ1[7:0] Coarse GMQ DAC Read-Out1 GmQ = GMQ0[6:0] + (number of 1’s in GMQ1[7:0] and GMQ2[6:0]) × 128 0x00 to 0x07 0xFF
GMQ2[6:0] Coarse GMQ DAC Read-Out2
0x00 to 0x07 0x01
GOR
Gain Out of Range
For DG < –19 GOR = 1; Else GOR = 0
0, 1
0
GPI0[6:0]
Fine GPI DAC Read-Out
BBPI input stage gain GpI.
0x00 to 0x7F 0x08
GPI1[7:0]
Coarse GPI DAC Read-Out1 GpI = GPI0[6:0] + (number of 1’s in GPI1[7:0] and GPI2[6:0]) × 128
0x00 to 0x07 0xFF
GPI2[6:0]
Coarse GPI DAC Read-Out2
0x00 to 0x07 0x01
GPQ0[6:0] Fine GPQ DAC Read-Out
BBPQ input stage gain GpQ.
0x00 to 0x7F 0x08
GPQ1[7:0] Coarse GPQ DAC Read-Out1 GpQ = GPQ0[6:0] + (number of 1’s in GPQ1[7:0] and GPQ2[6:0]) × 128
0x00 to 0x07 0xFF
GPQ2[6:0] Coarse GPQ DAC Read-Out2
0x00 to 0x07 0x01
IDT[3:0]
RF Buffer Bias
0x00 to 0x0D 0x04
IQGR[7:0]
I/Q Gain Ratio Control
Adjust the gain difference in approximate constant steps in dB. See Table 4. 0x00 to 0xFF 0x80
IQPHE[2:0] I/Q Phase Extension Bits
Extend the IQ phase adjustment range. See Table 9.
0x00 to 0x07 0x00
IQPHF[4:0]
Fine I/Q Phase Balance
Control
Fine adjustment of IQ LO phase difference. See Table 9. Zero phase shift for 0x00 to 0x1F 0x10
0x10.
IQPHSIGN
Sign IQ Phase Extension Bits Encodes the sign of the IQ phase extension bits IQPHE[2:0]. Positive for
IQPHSIGN = 1.
0, 1
0
OFFSETI[7:0] I-Channel Offset Control
Adjusts DC offset in the I-channel. Zero offset for 0x80. See page 19.
0x01 to 0xFF 0x80
OFFSETQ[7:0] Q-Channel Offset Control
Adjusts DC offset in the Q-channel. Zero offset for 0x80. See page 19.
0x01 to 0xFF 0x80
QDISABLE Disable Q-Channel
QDISABLE = 1 shuts down the Q-channel, turning the LTC5599 into an
upconversion mixer.
0, 1
0
SRESET
Soft Reset
Writing 1 to this bit resets all registers to their default values.
0, 1
0
TEMP[3:0] Thermometer Output
Digital representation of die temperature. Step size about 10°C.
0x00 to 0x07 0x07
TEMPCORR Temperature Correction
Disable
TEMPCORR = 1 disables temperature correction of the gain, and enables
manual fine-adjustment using bits GAINF[3:0].
0, 1
0
TEMPUPDT Temperature Correction
TEMPUPDT = 1 synchronizes temperature correction of the gain to a LOW
0, 1
1
Update
- HIGH transition on the TTCK pin. Asynchronous correction for TEMPUPDT
= 0.
THERMINP Thermometer Input Select For test purposes only. Should be set to 0.
0
0
5599f
40
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