LTC5800-IPR View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5800-IPR' PDF : 28 Pages View PDF
Advanced Information
5.0 Pinout
5.1
Eterna Mote-on-Chip
Figure 10 and Table 1 show the default pinout and pin-assignment for Eterna. For clarity the pins are grouped by function in
the pin-assignment table. In some cases, a pin may have multiple possible functions; the behavior is determined by the
software application layer.
Note: All unused input pins not configured with a pull resistor (see Pull column in pinout table) must be driven to their
inactive state or be configured by the Fuse Table to pull to an inactive state to avoid excess leakage and undesired operation.
Leakage due to floating inputs can be substantially greater than Eterna’s average power consumption. Pin functions shown in
gray are not currently supported via software.
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
RADIO_INHIBIT / GPIO15 1
54 VPP
CAP_PA_1P 2
53 SPIS_SSn / SDA
CAP_PA_1M 3
52 SPIS_SCK / SCL
CAP_PA_2M 4
51 GPIO26 / SPIS_MOSI / UARTC1_RX
CAP_PA_2P 5
50 SPIS_MISO / 1-Wire / UARTC1_TX
CAP_PA_3P 6
49 PWM0 / GPIO16
CAP_PA_3M 7
48 GPIO20
CAP_PA_4M 8
47 SPIM_SS_0n / GPIO12
CAP_PA_4P 9
Paddle
46 SPIM_SS_1n / GPIO13
VDDPA 10
(GND)
45 IPCS_SSn / GPIO3
LNA_EN / GPIO17 11
44 IPCS_SCK / GPIO4
RADIO_TX / GPIO18 12
43 SPIM_SCK / GPIO9
RADIO_TXn / GPIO19 13
42 IPCS_MOSI / GPIO5
ANTENNA 14
41 SPIM_MOSI / GPIO10
AI_0 15
40 IPCS_MISO / GPIO6
AI_1 16
39 SPIM_MISO / GPIO11
AI_3 17
38 UARTC0_RX
AI_2 18
37 UARTC0_TX
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Figure 10 Eterna Mote-on-Chip Pinout – Top View
12
Linear Technology / Dust Networks
Eterna Datasheet
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