LTC5800-IPR View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5800-IPR' PDF : 28 Pages View PDF
Advanced Information
No
CLI
Type
I/O
Pull
Description
37 UARTC0_TX
38 UARTC0_RX
2
O
-
CLI UART 0 transmit
1
I
UP CLI UART 0 receive
No
IPCS SPI
/FLASH
Programming
Type
I/O
Pull
Description
40 IPCS_MISO
2
O
-
SPI flash emulation (MISO) master in slave out port
42 IPCS_MOSI
1
I
-
SPI flash emulation (MOSI) master out slave in port
44 IPCS_SCK
1
I
-
SPI flash emulation (SCK) serial clock port
45 IPCS_SSn
1
I
-
SPI flash emulation slave select, active low
55 FLASH_P_ENn
1
I
UP Flash program enable, active low
Note that this functionality is available only when
RESETn is asserted
No
UART
Type
I/O
Pull
Description
66 UART_RX_RTSn
1*
I
-
UART receive (RTS) request to send, active low
67 UART_RX_CTSn
1
O
-
UART receive (CTS) clear to send, active low
68 UART_RX
1*
I
-
UART receive
69 UART_TX_RTSn
1
O
-
UART transmit (RTS) request to send, active low
70 UART_TX_CTSn
1*
I
-
UART transmit (CTS) clear to send, active low
71 UART_TX
2
O
-
UART transmit
* Input signals that must be driven or pulled to a valid state to avoid leakage.
5.3
Power Supply
Eterna is powered from a single pin, VSUPPLY, and generates all required supplies internally. With two integrated DC/DC
converters and four voltage regulators, the sensitivity to noise on VSUPPLY is minimal. However, during typical operation
Eterna will vary its load on the power supply from the μA range to 10’s of mA over a few μs. During such transients, the
power supply must meet the specifications for supply noise tolerance. Eterna is designed to operate with specific decoupling
capacitance on VCORE, VDDA, VOSC, VDDPA, and VPRIME, as well as the internal converter capacitors C1 through C4.
Failure to use correctly sized ceramic capacitors can result in supply instability and performance degradation.
5.3.1
Antenna
Eterna allows direct connection to a single-ended 50-Ohm antenna; an internal TX/RX switch simplifies external circuitry
requirements. Because both the transmit and the receive paths are single-ended, a balun (with its associated cost and
efficiency loss) are not required. Eterna provides options to set typical output power to 0 dBm or to +8 dBm using the on-chip
PA. For further details on radio transmit and receive, see section 2.4.
5.5
JTAG
Eterna includes an IEEE 1149.1-compliant JTAG port for boundary scan.
14
Linear Technology / Dust Networks
Eterna Datasheet
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