LTC6803-2/LTC6803-4
OPERATION
Table 11. Cell Voltage (CV) Register Group
REGISTER RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
CVR00
RD
C1V[7]
C1V[6]
C1V[5]
C1V[4]
C1V[3]
CVR01
RD
C2V[3]
C2V[2]
C2V[1]
C2V[0]
C1V[11]
CVR02
RD
C2V[11]
C2V[10]
C2V[9]
C2V[8]
C2V[7]
CVR03
RD
C3V[7]
C3V[6]
C3V[5]
C3V[4]
C3V[3]
CVR04
RD
C4V[3]
C4V[2]
C4V[1]
C4V[0]
C3V[11]
CVR05
RD
C4V[11]
C4V[10]
C4V[9]
C4V[8]
C4V[7]
CVR06
RD
C5V[7]
C5V[6]
C5V[5]
C5V[4]
C5V[3]
CVR07
RD
C6V[3]
C6V[2]
C6V[1]
C6V[0]
C5V[11]
CVR08
RD
C6V[11]
C6V[10]
C6V[9]
C6V[8]
C6V[7]
CVR09
RD
C7V[7]
C7V[6]
C7V[5]
C7V[4]
C7V[3]
CVR10
RD
C8V[3]
C8V[2]
C8V[1]
C8V[0]
C7V[11]
CVR11
RD
C8V[11]
C8V[10]
C8V[9]
C8V[8]
C8V[7]
CVR12
RD
C9V[7]
C9V[6]
C9V[5]
C9V[4]
C9V[3]
CVR13
RD
C10V[3]
C10V[2]
C10V[1]
C10V[0]
C9V[11]
CVR14
RD
C10V[11] C10V[10]
C10V[9]
C10V[8]
C10V[7]
CVR15*
RD
C11V[7]
C11V[6]
C11V[5]
C11V[4]
C11V[3]
CVR16*
RD
C12V[3]
C12V[2]
C12V[1]
C12V[0]
C11V[11]
CVR17*
RD
C12V[11] C12V[10]
C12V[9]
C12V[8]
C12V[7]
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low
Table 12. Flag (FLG) Register Group
REGISTER RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
FLGR0
RD
C4OV
C4UV
C3OV
C3UV
C2OV
FLGR1
RD
C8OV
C8UV
C7OV
C7UV
C6OV
FLGR2
RD
C12OV*
C12UV*
C11OV*
C11UV*
C10OV
* Bits C11UV, C12UV, C11OV and C12OV are always low if the CELL10 bit in register CFGR0 is high
BIT 2
C1V[2]
C1V[10]
C2V[6]
C3V[2]
C3V[10]
C4V[6]
C5V[2]
C5V[10]
C6V[6]
C7V[2]
C7V[10]
C8V[6]
C9V[2]
C9V[10]
C10V[6]
C11V[2]
C11V[10]
C12V[6]
BIT 2
C2UV
C6UV
C10UV
BIT 1
C1V[1]
C1V[9]
C2V[5]
C3V[1]
C3V[9]
C4V[5]
C5V[1]
C5V[9]
C6V[5]
C7V[1]
C7V[9]
C8V[5]
C9V[1]
C9V[9]
C10V[5]
C11V[1]
C11V[9]
C12V[5]
BIT 1
C1OV
C5OV
C9OV
Table 13. Temperature (TMP) Register Group
REGISTER RD/WR
BIT 7
BIT 6
TMPR0
RD
ETMP1[7] ETMP1[6]
TMPR1
RD
ETMP2[3] ETMP2[2]
TMPR2
RD
ETMP2[11] ETMP2[10]
TMPR3
RD
ITMP[7]
ITMP[6]
TMPR4
RD
NA
NA
BIT 5
ETMP1[5]
ETMP2[1]
ETMP2[9]
ITMP[5]
NA
BIT 4
ETMP1[4]
ETMP2[0]
ETMP2[8]
ITMP[4]
THSD
BIT 3
ETMP1[3]
ETMP1[11]
ETMP2[7]
ITMP[3]
ITMP[11]
BIT 2
ETMP1[2]
ETMP1[10]
ETMP2[6]
ITMP[2]
ITMP[10]
BIT 1
ETMP1[1]
ETMP1[9]
ETMP2[5]
ITMP[1]
ITMP[9]
BIT 0
C1V[0]
C1V[8]
C2V[4]
C3V[0]
C3V[8]
C4V[4]
C5V[0]
C5V[8]
C6V[4]
C7V[0]
C7V[8]
C8V[4]
C9V[0]
C9V[8]
C10V[4]
C11V[0]
C11V[8]
C12V[4]
BIT 0
C1UV
C5UV
C9UV
BIT 0
ETMP1[0]
ETMP1[8]
ETMP2[4]
ITMP[0]
ITMP[8]
Table 14. Packet Error Code (PEC)
REGISTER RD/WR
BIT 7
PEC
RD
PEC[7]
Table 15. Diagnostic Register Group
REGISTER RD/WR
BIT 7
DGNR0
RD
REF[7]
DGNR1
RD
REV[1]
BIT 6
PEC[6]
BIT 6
REF[6]
REV[0]
24
BIT 5
PEC[5]
BIT 5
REF[5]
MUXFAIL
BIT 4
PEC[4]
BIT 4
REF[4]
NA
BIT 3
PEC[3]
BIT 3
REF[3]
REF[11]
BIT 2
PEC[2]
BIT 2
REF[2]
REF[10]
BIT 1
PEC[1]
BIT 1
REF[1]
REF[9]
BIT 0
PEC[0]
BIT 0
REF[0]
REF[8]
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