LTC6803-2 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC6803-2' PDF : 40 Pages View PDF
LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
HARDWARE SHUTDOWN
To completely shut down the LTC6803 a PMOS switch can
be connected to V+, or, V+ can be driven from an isolated
power supply. Figure 23 shows an example of a switched
V+. The breakdown voltage of DZ4 is about 1.8V. If SHDN <
1.8V, no current will flow through the stacked MMBTA42s
and the 1M resistors. TP0610Ks will be completely shut
off. If SHDN > 2.5V, M7 will be turned on and then all
TP0610Ks will be turned on.
PCB LAYOUT CONSIDERATIONS
The VREG and VREF pins should be bypassed with a 1µF
capacitor for best performance. The LTC6803 is capable of
operation with as much as 55V between V+ and V–. Care
should be taken on the PCB layout to maintain physical
separation of traces at different potentials. The pinout
of the LTC6803 was chosen to facilitate this physical
separation. There is no more than 5.5V between any two
adjacent pins. The package body is used to separate the
highest voltage (e.g., 43.2V) from the lowest voltage (0V).
TP0610K
V+
C12
LTC6803-4
IC #3
C0
V–
TP0610K
V+
C12
LTC6803-4
IC #2
C0
V–
TP0610K
V+
C12
LTC6803-4
IC #1
C0
V–
+
DZ1
15V
1M
+
D1 +
+
DZ2
15V
1M
+
D2 +
DZ3
15V
1M
+
SHDN +
DZ4
1.8V
+
50k
680324 F23
DZ1, DZ2, DZ3: MMSZ5245B
DZ4: MMSZ4678T1
ALL NPN: MMBTA42
ALL PN: RS07J
Figure 23. Hardware Shutdown Circuit Reduces Total Supply
Current of LTC6803-4 to About 0µA
680324f
36
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