LTC6803 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC6803' PDF : 40 Pages View PDF
APPLICATIONS INFORMATION
SUPPLY DECOUPLING IF BATTERY-STACK POWERED
As shown in Figure 23, the LTC6803-3 can have filtering
on both V+ and V–, so differential bypassing to the cell
group potentials is recommended. The Zener suppresses
overvoltages from reaching the IC supply pins. A small
ferrite-bead inductor provides protection for the Zener, par-
ticularly from energetic ESD strikes. Since the LTC6803-1
cannot have a series resistance to V–, additional Schottky
diodes are needed to prevent ESD-induced reverse-supply
(substrate) currents to flow.
LTC6803-1/LTC6803-3
+
+ BATTERY
STACK
+
+
R
ISUPPLY
LTC6803-1
C1
V–
+
+ BATTERY
STACK
+
LTC6803-3
+
C1
R
ISUPPLY
C0
V–
680313 F24
Figure 24. Kelvin Connection on C0 Improving
Bottom Cell Voltage Measurement Accuracy
BLM31PG330SN1L
CELLGROUP+
100Ω
V+
CMHZ5265B
CELLGROUP–
BAT46W
LTC6803-1 Configuration
100nF
V–
680313 F23
BLM31PG330SN1L
CELLGROUP+
100Ω
V+
CMHZ5265B
CELLGROUP–
100Ω
100nF
V–
LTC6803-3 Configuration
Figure 23. Supply Decoupling
ADVANTAGES OF KELVIN CONNECTION ON C0
The V– trace resistance can cause an observable voltage
drop between the negative end of the bottom battery
cell and V– pin of LTC6803. This voltage drop will add
to the measurement error of the bottom cell voltage for
LTC6803‑1. The LTC6803-3 separates C0 from V–, allow-
ing Kelvin connection on C0 as shown in Figure 24. Any
voltage drop on V– trace will not affect the bottom cell
voltage measurement. The Kelvin connection will also
allow RC filtering on V– as shown in Figure 23.
HARDWARE SHUTDOWN
To completely shut down the LTC6803 a PMOS switch can
be connected to V+, or V+ can be driven from an isolated
power supply. Figure 25 shows an example of a switched
V+. The breakdown voltage of DZ4 is about 1.8V. If SHDN <
1.8V, no current will flow through the stacked MMBTA42s
and the 1M resistors. TP0610Ks will be completely shut
off. If SHDN > 2.5V, M7 will be turned on and all TP0610Ks
will be turned on.
Figure 26 is an example of isolated power supply. This
circuit provides power for two LTC6803s used to monitor
24 series connected battery cells. When 5V is removed, the
LTC6803s will draw 1nA from the battery cells. Note that
use of an external V+ supply will not protect daisy-chain
SPI operation at low total stack potentials (below 5V).
PCB LAYOUT CONSIDERATIONS
The VREG and VREF pins should be bypassed with a 1µF
capacitor for best performance. The LTC6803 is capable of
operation with as much as 55V between V+ and V–. Care
should be taken on the PCB layout to maintain physical
separation of traces at different potentials. The pinout of
680313f
35
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