M24128-BN5T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24128-BN5T' PDF : 17 Pages View PDF
M24256, M24128
Figure 4. I2C Bus Protocol
SCL
SDA
START
Condition
SDA
Input
SDA
Change
STOP
Condition
SCL
SDA
1
2
3
MSB
START
Condition
7
8
9
ACK
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
Condition
AI00792B
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9th bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
Table 3. Device Select Code 1
Device Type Identifier
b7
b6
b5
b4
Device Select Code
1
0
1
0
Note: 1. The most significant bit, b7, is sent first.
4/17
Chip Enable
RW
b3
b2
b1
b0
0
0
0
RW
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