M24128-BN5T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24128-BN5T' PDF : 17 Pages View PDF
M24256, M24128
Table 4. Operating Modes
Mode
RW bit
Current Address Read
1
0
Random Address Read
1
Sequential Read
1
Byte Write
0
Page Write
0
Note: 1. X = VIH or VIL.
WC 1
X
X
X
X
VIL
VIL
Data Bytes
Initial Sequence
1
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
1
reSTART, Device Select, RW = ‘1’
≥1
Similar to Current or Random Address Read
1
START, Device Select, RW = ‘0’
≤ 64 START, Device Select, RW = ‘0’
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
BYTE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01120C
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