M24512-x, M24256-Bx
DC and AC parameters
Table 16. AC characteristics (M24xxx-W, M24xxx-R, M24256-BF see Table 8, Table 9
Table 10 and Table 11)
Symbol Alt.
Parameter
Min.
Max. Unit
fC
fSCL Clock frequency
400
kHz
tCHCL
tHIGH Clock pulse width high
600
ns
tCLCH
tDL1DL2(1)
tXH1XH2(2)
tXL1XL2(2)
tLOW
tF
tR
tF
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
1300
ns
20
100
ns
20
300
ns
20
300
ns
tDXCX tSU:DAT Data in set up time
100
ns
tCLDX tHD:DAT Data in hold time
0
ns
tCLQX
tCLQV(3)
tCHDX(4)
tDH
tAA
tSU:STA
Data out hold time
Clock low to next data valid (access time)
Start condition set up time
200
ns
200
900
ns
600
ns
tDLCL tHD:STA Start condition hold time
600
ns
tCHDH tSU:STO Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
tWR Write time
tNS
Pulse width ignored (input filter on SCL and
SDA) - single glitch
5
ms
100
ns
1. Sampled only, not 100% tested.
2. Values recommended by I²C-bus/Fast-Mode specification.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. For a re-Start condition, or following a Write cycle.
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