M24256-BRBN6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M24256-BRBN6
STMicroelectronics
'M24256-BRBN6' PDF : 37 Pages View PDF
DC and AC parameters
M24512-x, M24256-Bx
Table 17. 1 MHz AC characteristics (M24xxx-HR, see Table 9 and Table 11)
Test conditions specified in Table 9
Symbol Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
MHz
tCHCL
tHIGH Clock pulse width high
300
-
ns
tCLCH
tXH1XH2(1)
tXL1XL2(1)
tDL1DL2(2)
tLOW
tR
tF
tF
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
400
-
ns
20
300
ns
20
300
ns
20
100
ns
tDXCX
tSU:DAT Data in setup time
80
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX
tDH Data out hold time
50
-
ns
tCLQV(3)(4)
tAA Clock low to next data valid (access time) 50
500
ns
tCHDX(5)
tSU:STA Start condition setup time
250
-
ns
tDLCL
tHD:STA Start condition hold time
250
-
ns
tCHDH
tSU:STO Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next
Start condition
500
-
ns
tW
tNS(2)
tWR
Write time
-
Pulse width ignored (input filter on SCL and
SDA)
-
5
ms
50
ns
1. Values recommended by the I²C-bus Fast-Mode specification.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming
that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 5).
5. For a reStart condition, or following a Write cycle.
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