M24C02-DRMF3G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24C02-DRMF3G' PDF : 39 Pages View PDF
M24C02-A125
DC and AC parameters
Table 12. 1 MHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max. Unit
fC
fSCL Clock frequency
0
tCHCL
tHIGH Clock pulse width high
260
tCLCH
tLOW Clock pulse width low
500
tXH1XH2
tR Input signal rise time
(1)
tXL1XL2
tF Input signal fall time
(1)
tQL1QL2 (2)
tF SDA (out) fall time
20
tDXCH
tSU:DAT Data in setup time
50
tCLDX
tHD:DAT Data in hold time
0
tCLQX (3)
tDH Data out hold time
100
tCLQV (4)
tAA Clock low to next data valid (access time)
-
tCHDL
tSU:STA Start condition setup time
250
tDLCL
tHD:STA Start condition hold time
250
tCHDH
tSU:STO Stop condition setup time
250
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
tWLDL(5) (2) tSU:WC WC set up time (before the Start condition)
0
tDHWH(6) (2) tHD:WC WC hold time (after the Stop condition)
1
tW
tWR Write time
-
tNS (2)
-
Pulse width ignored (input filter on SCL and
SDA)
-
1
MHz
-
ns
-
ns
(1)
ns
(1)
ns
120
ns
-
ns
-
ns
-
ns
450
ns
-
ns
-
ns
-
ns
-
ns
-
µs
-
µs
4
ms
80
ns
1. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC < 1 MHz.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4.
taCsLsQuVmisintghethtaimt tehe(frRobmusth×e
falling edge of SCL)
Cbus time constant
required by
is within the
the SDA bus line
values specified
to
in
reach either
Figure 11.
0.3
VCC
or
0.7
VCC,
5. WC=0 set up time condition to enable the execution of a WRITE command.
6. WC=0 hold time condition to enable the execution of a WRITE command.
DocID025755 Rev 5
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