M25PX32 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M25PX32' PDF : 63 Pages View PDF
M25PX32
Instructions
6.4.4
6.4.5
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status
Register (WRSR) instruction provided that the Write Enable (WREN) instruction has been
issued. The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1,
BP2) bits to determine if the protected area defined by the Block Protect bits starts from the
top or the bottom of the memory array:
● When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits
starts from the top of the memory array (see Table 3: Protected area sizes)
● When TB is set to ‘1’, the area protected by the Block Protect bits starts from the
bottom of the memory array (see Table 3: Protected area sizes)
The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status
Register Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
C
DQ0
DQ1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
Status Register Out
Status Register Out
76543210765432107
MSB
MSB
AI13734
29/63
Share Link: 
