M29W800B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M29W800B
STMicroelectronics
'M29W800B' PDF : 33 Pages View PDF
M29W800T, M29W800B
Figure 7. Write AC Waveforms, W Controlled
A0-A18/
A–1
E
G
W
DQ0-DQ7/
DQ8-DQ15
tAVWL
tELWL
tGHWL
tAVAV
VALID
tWLAX
tWHEH
tWHGL
tWLWH
tDVWH
VALID
tWHWL
tWHDX
VCC
RB
tVCHEL
tWHRL
AI02183
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
During the executionof the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
ChipErase (CE) Instruction. This instructionuses
six write cycles. The Erase Set-up command 80h
is written to address AAAAh in the Byte-wide con-
figuration or the address 5555h in the Word-wide
configurationon the third cycle after the two Coded
cycles. The Chip Erase Confirm command 10h is
similarly written on the sixth cycle after anothertwo
Coded cycles. If the second command given is not
an erase confirm or if the Coded cycles are wrong,
the instruction aborts and the device is reset to
Read Array. It is not necessaryto programthe array
with 00h firstas theP/E.C. will automaticallydo this
before erasing it to FFh. Read operations after the
sixth rising edge of W or E output the Status
Register bits. During the execution of the erase by
the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’
on completion. The Toggle bits DQ2 and DQ6
toggle during erase operation and stop when erase
is completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure.
21/33
Share Link: 