M40SZ100Y, M40SZ100W
Figure 7. Power up timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
E
ECON
RST
tRB
VOHB
tR
tCER
tREC
tEPD
Operation
tEPD
PFO
VALID
AI03937
Table 2.
Symbol
Power down/up AC characteristics
Parameter(1)
Min
Max Unit
tF(2)
tFB(3)
tPFD
tR
tEPD
VPFD (max) to VPFD (min) VCC fall time
VPFD (min) to VSS VCC fall time
PFI to PFO propagation delay
VPFD(min) to VPFD (max) VCC rise time
Chip enable propagation delay (low or high)
M40SZ100Y
M40SZ100W
300
µs
10
µs
15
25
µs
10
µs
10
ns
15
ns
tRB
tCER
tREC
tWPT
VSS to VPFD (min) VCC rise time
Chip enable recovery
VPFD (max) to RST high
Write protect time
1
µs
40
120
ms
40
200
ms
40
200
µs
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
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