M41ST87YMX6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M41ST87YMX6TR
STMicroelectronics
'M41ST87YMX6TR' PDF : 42 Pages View PDF
M41ST87Y, M41ST87W
Avoiding Inadvertent Tampers (Normally
Closed Configuration)
In some applications it may be necessary to use a
low pass filter to reduce electrical noise on the
Tamper Input pin when the TCMX Bit = 0 (Normally
Closed). This is especially true if the tamper detect
switch is located some distance (> 6”) from the
Tamper Input pin. A low pass filter can prevent un-
wanted, higher frequency noise from inadvertently
being detected as a tamper condition caused by
the “antenna-effect” (produced by a longer signal
wire or mesh). This low pass filter can be con-
structed using a series resistor (R) in conjunction
with a capacitor (C) on the Tamper Input pin.
The cut-off frequency fc is determined according to
the formula:
fc = 1 ⁄ (2 ⋅ Pi ⋅ R ⋅ C)
Figure 21. Low Pass Filter Implementation for
Noise Immunity
To Tamper Detect Switch
R
TPIN
C
AI11185
Table 6. Calculated Cut-off Frequency for Typical Capacitance and Resistance Values
R (Ω)
C (F)
fc
1/fc (s)
1000
1.00E-09
15.9MHz
6.28µs
1000
1.00E-06
159.2Hz
6.28ms
5000
1.00E-09
31.8kHz
31.4µs
5000
1.00E-06
31.8Hz
31.4ms
10000
1.00E-09
15.9kHz
62.8µs
10000
1.00E-06
15.9Hz
62.8ms
Tamper Event Time-Stamp
Regardless of which tamper occurs first, not only
will the appropriate Tamper Bit be set, but the
event will also be automatically time-stamped.
This is accomplished by freezing the normal up-
date of the clock registers (00h through 07h) im-
mediately following a tamper event. Thus, when
tampering occurs, the user may first read the time
registers to determine exactly when the tamper
event occurred, then re-enable the clock update to
the current time (and reset the Tamper Bit, TBX) by
resetting the Tamper Enable Bit (TEBX).
The time update will then resume and the clock
can be read to determine the current time. Both
Tamper Enable Bits (TEBX) must always be set to
'0' in order to read the current time.
In the event of multiple tampers, the Time-Stamp
will reflect the initial tamper event.
Note: If the TEBX Bit is set, the Tamper Event
Time-Stamp will take precedence over the Power
Down Time-Stamp (see Power-Down Time-
Stamp, page 24) and the HT Bit (Halt Update) will
not be set during the power-down event. If both
are needed, the Power Down Time-Stamp may be
accomplished by writing the time into the General
Purpose RAM memory space when PFO is assert-
ed.
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