M41T00S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T00S' PDF : 26 Pages View PDF
M41T00S
Clock operation
Table 2. TIMEKEEPER® register map
Addr
D7
D6
D5
D4
D3
D2
D1
D0
00h
ST
10 seconds
Seconds
01h
OF
10 minutes
Minutes
02h CEB CB
10 hours
Hours (24-hour format)
03h
0
0
0
0
0
Day of week
04h
0
0
10 date
Date: day of month
05h
0
0
0
10M
Month
06h
10 years
Year
07h OUT FT
S
Calibration
Keys:
0 = must be set to '0'
CB = century bit
CEB = century enable bit
FT = frequency test bit
OF = oscillator fail bit
OUT = output level
S = sign bit
ST = stop bit
Function/range BCD format
Seconds
Minutes
Century/hours
Day
Date
Month
Year
Calibration
00-59
00-59
0-1/00-23
01-7
01-31
01-12
00-99
3.2
Calibrating the clock
The M41T00S is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error
at 25oC, which equates to about ±1.53 minutes per month (see Figure 10 on page 15).
When the calibration circuit is properly employed, accuracy improves to better than ±2 ppm
at 25°C.
The oscillation rate of crystals changes with temperature. The M41T00S design employs
periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 15. The
number of times pulses which are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
calibration register. Adding counts speeds the clock up, subtracting counts slows the clock
down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 07h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
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