M41T62 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T62' PDF : 33 Pages View PDF
Operation
M41T62/63/64/65
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is
shown in Figure 19 on page 16. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T6x slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see Figure 16 on page 14 and again after it has received the word address and each data
byte.
Figure 19. WRITE mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+X P
AI00591
16/41
Doc ID 10397 Rev 14
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