M41T62 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T62' PDF : 41 Pages View PDF
M41T62/63/64/65
Clock operation
3.4
Note:
Note:
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution
where:
000=1/16 second (16 Hz);
001=1/4 second (4 Hz);
010=1 second (1 Hz);
011=4 seconds (1/4 Hz); and
100 = 1 minute (1/60 Hz).
Invalid combinations (101, 110, and 111) will NOT enable a watchdog time-out. Setting
BMB4-BMB0 = 00000 with any combination of RB2-RB0, other than 000, will result in an
immediate watchdog time-out.
The amount of time-out is then determined to be the multiplication of the five-bit multiplier
value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3
seconds). If the processor does not reset the timer within the specified period, the M41T6x
sets the WDF (watchdog flag) and generates an interrupt on the IRQ pin (M41T62), or a
watchdog output pulse (M41T63 and M41T65 only) on the WDO pin. The watchdog timer
can only be reset by having the microprocessor perform a WRITE of the watchdog register.
The time-out period then starts over.
Should the watchdog timer time-out, any value may be written to the watchdog register in
order to clear the IRQ pin. A value of 00h will disable the watchdog function until it is again
programmed to a new value. A READ of the flags register will reset the watchdog flag (bit
D7; register 0Fh). The watchdog function is automatically disabled upon power-up, and the
watchdog register is cleared.
A WRITE to any clock register will restart the watchdog timer.
3.5
Note:
Watchdog output (WDO - M41T63/65 only)
If the processor does not reset the watchdog timer within the specified period, the watchdog
output (WDO) will pulse low for trec (see Table 18 on page 35). This output may be
connected to the reset input of the processor in order to generate a processor reset. After a
watchdog time-out occurs, the timer will remain disabled until such time as a new
countdown value is written into the watchdog register.
The crystal oscillator must be running for the WDO pulse to be available.
The WDO output is an N-channel, open drain output driver (with IOL as specified in Table 14
on page 33).
Doc ID 10397 Rev 14
27/41
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