M41T62 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T62' PDF : 41 Pages View PDF
M41T62/63/64/65
Clock operation
3.8
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all
leap years correctly. See Table 10 on page 30 for additional explanation.
3.9
Note:
Output driver pin (M41T62/65)
When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the
IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the calibration
register. In other words, when D7 (OUT Bit) is a '0,' then the IRQ/OUT pin will be driven low.
The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.10
Note:
Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator.
The following conditions can cause the OF bit to be set:
● The first time power is applied (defaults to a '1' on power-up).
If the OF bit cannot be written to '0' four (4) seconds after the initial power-up, the STOP bit
(ST) should be written to a '1,' then immediately reset to '0.'
● The voltage present on VCC or battery is insufficient to support oscillation.
● The ST bit is set to '1.'
● External interference of the crystal
If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ pin will also be activated.
The IRQ output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading the flag
register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event
occurs during a power-down condition, this bit will be set correctly.
3.11
Initial power-on defaults
Upon application of power to the device, the register bits will initially power-on in the state
indicated in Table 9.
Doc ID 10397 Rev 14
29/41
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