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M41T81 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
M41T81
STMICROELECTRONICS
STMicroelectronics STMICROELECTRONICS
'M41T81' PDF : 29 Pages View PDF
M41T81
Clock operation
3.8
Note:
Output driver pin
When the FT bit, AFE bit, SQWE bit, and watchdog register are not set, the
IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
control register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 08h
are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
3.9
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state:
watchdog register; AFE; ABE; SQWE; and FT. The following bits are set to a '1' state: ST;
OUT; and HT (see Table 5).
Table 5. Preferred default values
Condition
ST
HT
OUT
FT
AFE SQWE ABE
Watchdog
register(1)
Initial power-up(2)
1
1
1
0
0
0
0
0
Subsequent power-up (with
battery backup)(3)
UC
1
UC
0
UC UC UC
0
1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = unchanged
Doc ID 7529 Rev 10
19/29
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