M7010R View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M7010R' PDF : 67 Pages View PDF
M7010R
Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM
DQ
DQ
[67:30]
[29]
DQ
[28:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:14]
DQ
[13:0]
Successful
SEARCH
Reserved
0: Direct
1: Indirect
Register Index
(Applicable if
ID
DQ[29] is
indirect)
00: Data
Array
Reserved
If DQ[29] is '0,' this field carries the
address of the data array location.
If DQ[29] is '1,' the SSR specified on
DQ[28:26] is used to generate the
address of the data array location:
{SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.(1)
If DQ[29] is '0,' this field carries
Successful
address of the mask array location.
SEARCH
If DQ[29] is '1,' the SSR specified on
Reserved
0: Direct
1: Indirect
Register Index
(Applicable if
ID
01: Mask
Array
Reserved DQ[28:26] is used to generate the
address of the data array location:
DQ[29] is
{SSR[13:2], SSR[1] | DQ[1], SSR[0]
indirect)
| DQ[0]}.(1)
Reserved
0: Direct
1: Indirect
Successful
SEARCH
Register Index
(Applicable if
DQ[29] is
indirect)
If DQ[29] is '0,' this field carries
address of the data SRAM location.
If DQ[29] is '1,' the SSR specified on
ID
10: External
SRAM
Reserved
DQ[28:26] is used to generate the
address of the data array location:
{SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.(1)
Note: 1. “|” stands for logical OR operation, and “{ }” stands for concatenation operator.
Table 23. WRITE Address Format for Internal Registers
DQ[67:26]
DQ[25:21]
DQ[20:19]
DQ[18:6]
Reserved
ID
11: Register
Reserved
DQ[5:0]
Register address
Table 24. WRITE Address Format for Data and Mask Array (Burst WRITE)
DQ
[67:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:14]
DQ
[13:0]
Reserved
Don’t care. These 14 bits come from the
ID
00: Data array
Reserved internal register (WBURADR), which
increments with each access.
Reserved
Don’t care. These 14 bits come from the
ID
01: Mask array Reserved internal register (WBURADR), which
increments with each access.
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