M7010R
Figure 37. LEARN Timing Diagram on Device Number 7 (TLSZ = 01)
CLK 2X
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10
1
3
5
7
9
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
Learn1 X Learn2 X
Comp1
Comp2
AB X
X
DQ
SADR[21:0]
X
X
1A 1B
X
X
ALE_L, CE_L
1
WE_L
1
OE_L
0
SSV
0
SSF
0
TLSZ = 01, LRAM = 1, LDEV = 1
z
z
z
1
z1
z
1
z1
1
0
AI07047
Table 34. SRAM WRITE Cycle Latency from Second Cycle of LEARN Instruction
Number of Devices
Latency in CLK Cycles
1 (TLSZ = 00)
4
1-8 (TLSZ = 01)
5
1-31 (TLSZ = 10)
6
51/67