M95256-CS3G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95256-CS3G' PDF : 48 Pages View PDF
Instructions
M95256-DR, M95256, M95256-W, M95256-R
Figure 12. Page Write (WRITE) sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte 1
D
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
5.6.1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
Data Byte 3
Data Byte N
D
7654321076543210
6543210
AI01796D
1. The most significant address bit (b15) is Don’t Care.
ECC (error correction code) and Write cycling
The M95256 and M95256-D devices offer an ECC (error correction code) logic which
compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write data in words (4 bytes) in order to
optimize the number of Write cycles.
The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device in multiples of 4-byte words.
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Doc ID 12276 Rev 11
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