Instructions
M95256-DR, M95256, M95256-W, M95256-R
The instruction is not accepted, and so not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
● if Status register bits (BP1,BP0) = (1,1)
● if a write cycle is already in progress
● if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
● if the Identification page is locked by the Lock Status bit
Figure 16. Lock ID sequence
3
#
)NSTRUCTION
BIT ADDRESS
$ATA BYTE
$
(IGH IMPEDANCE
1
!I
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Doc ID 12276 Rev 11