M95320-DRE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95320-DRE' PDF : 41 Pages View PDF
DC and AC parameters
M95320-DRE
Table 13. AC characteristics
Min. Max. Min. Max. Min. Max.
Symbol Alt.
Parameter
Test
conditions
Test
conditions
Test
conditions
Unit
specified in specified in specified in
Table 10 Table 10 Table 11
fC
fSCK Clock frequency
-
5
- 10 - 20 MHz
tSLCH tCSS1 S active setup time
60 - 30 - 15 -
tSHCH tCSS2 S not active setup time
60 - 30 - 15 -
tSHSL
tCS S deselect time
90 - 40 - 20 -
tCHSH tCSH S active hold time
60 - 30 - 15 - ns
tCHSL
tCH(1)
tCL(1)
tCLCH(2)
tCHCL(2)
S not active hold time
tCLH Clock high time
tCLL Clock low time
tRC Clock rise time
tFC Clock fall time
60 - 30 - 15 -
80 - 40 - 20 -
80 - 40 - 20 -
-
2
-
2
-
2
µs
-
2
-
2
-
2
tDVCH tDSU Data in setup time
20 - 10 -
5
-
tCHDX
tDH Data in hold time
20 - 10 - 10 -
tHHCH
Clock low hold time after HOLD not active 60 - 30 - 15 -
tHLCH
Clock low hold time after HOLD active
60 - 30 - 15 -
tCLHL
Clock low set-up time before HOLD active
0
-
0
-
0
-
tCLHH
tSHQZ(2)
tCLQV(3)
Clock low set-up time before HOLD not
active
tDIS Output disable time
tV Clock low to output valid
0
-
0
-
0
-
-
80
-
40
-
20 ns
- 80 - 40 - 20
tCLQX
tQLQH(2)
tQHQL(2)
tHO Output hold time
tRO Output rise time
tFO Output fall time
0
-
0
-
0
-
- 20 - 20 - 20
- 20 - 20 - 20
tHHQV
tHLQZ(2)
tLZ HOLD high to output valid
tHZ HOLD low to output high-Z
- 80 - 40 - 20
- 80 - 40 - 20
tW
tWC Write time
-
4
-
4
-
4 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3.
t(CoLr QgVrematuesrt
be compatible with
than) tCLQV+tSU.
tCL
(clock
low
time):
if
tSU
is
the
Read
setup
time
of
the
SPI
bus
master,
tCL
must
be
equal
to
32/42
DocID027471 Rev 2
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