M95320-R View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95320-R' PDF : 48 Pages View PDF
Instructions
M95320-W M95320-R M95320-DR
Note:
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
● if a Write cycle is already in progress,
● if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 13. Page Write (WRITE) sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte 1
D
15 14 13
321076543210
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
Data Byte 3
Data Byte N
D
7654321076543210
6543210
AI01796D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
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Doc ID 5711 Rev 14
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