MAS 35x9F
DATA SHEET
Flash
µC
VSENS1
DC/DC 1
on
I2CVDD
I2C
XVDD
VDD
VSENS2
DC/DC 2
on
DSP
e.g. 2.7 V
e.g. 2.2 V
AVDD0/1 Analog
Parts
Fig. 2–8: Solution 1: Power-optimized
Flash
VSENS1
DC/DC1
on
µC
I2CVDD
I2C
XVDD
VDD
VSENS2
DC/DC2
on
DSP
e.g. 2.7 V
e.g. 2.2 V
AVDD0/1 Analog
Parts
Fig. 2–9: Solution 2: Volume-optimized
Flash
e.g. 2.7 V
µC
VSENS1
DC/DC1
on
I2CVDD
I2C
XVDD
VDD
VSENS2
DC/DC2
off
DSP
AVDD0/1 Analog
Parts
Fig. 2–10: Solution 3: Minimized components
Flash
VSENS1
DC/DC1
off
µC
I2CVDD I2C
XVDD
VDD
VSENS2
DC/DC2
off
External
Supply
e.g. 2.7 V
AVDD0/1
Analog
Parts
DSP
Fig. 2–11: Solution 4: External power supply
14
June 30, 2004; 6251-505-1DS
Micronas