MC9S08SL8 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S08SL8' PDF : 356 Pages View PDF
Chapter 1 Device Overview
1.3 System Clock Distribution
Figure 1-3 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function.
The following defines the clocks used in this MCU:
• BUSCLK — The frequency of the bus is always half of ICSOUT.
• ICSOUT — Primary output of the ICS and is twice the bus frequency.
• ICSLCLK — Development tools can select this clock source to speed up BDC communications in
systems where the bus clock is configured to run at a very slow frequency.
• ICSERCLK — External reference clock can be selected as the RTC clock source and as the
alternate clock for the ADC module.
• ICSIRCLK — Internal reference clock can be selected as the RTC clock source.
• ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1 and TPM2
modules.
• LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules.
• TCLK — External input clock source for TPM1 and TPM2 and is referenced as TPMCLK in TPM
chapters.
1 kHZ
LPO
ICSERCLK
ICSIRCLK
TCLK
RTC
COP
TPM1
TPM2
SCI
SLIC
SPI
ICS
ICSFFCLK
÷2
FFCLK*
ICSOUT
ICSLCLK
÷2 BUSCLK
XOSC
CPU
BDC
ADC
IIC
EXTAL XTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one
half of the bus clock frequency.
ADC has min and max
frequency requirements.
See the ADC chapter
and electricals appendix
for details.
Figure 1-3. System Clock Distribution Diagram
FLASH EEPROM
FLASH and EEPROM
have frequency
requirements for program
and erase operation. See
the electricals appendix
for details.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
23
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