MC9S12E128MFC View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
MFG CO.
'MC9S12E128MFC' PDF : 156 Pages View PDF
Device User Guide — 9S12E12F8rDeGeV1s/DcVa0l1e.04Semiconductor, Inc.
SS1
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN2
12
12
BIT 6 . . . 1
9
(OUMTPOUSTI)PORT DATA
11
MASTER MSB OUT2 BIT 6 . . . 1
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
13
3
13
LSB IN
MASTER LSB OUT
PORT DATA
Figure B-5 SPI Master Timing (CPHA=1)
In Table B-8 the timing characteristics for master mode are listed.
Table B-8 SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
P SCK Frequency
P SCK Period
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid after SCK Edge
D Data Valid after SS fall (CPHA=0)
D Data Hold Time (Outputs)
D Rise and Fall Time Inputs
D Rise and Fall Time Outputs
Symbol
fsck
tsck
tlead
tlag
twsck
tsu
thi
tvsck
tvss
tho
trfi
trfo
Min
1/2048
2
—
—
—
8
8
—
—
20
—
—
Typ
—
—
1/2
1/2
1/2
—
—
—
—
—
—
—
Max
1/2
2048
—
—
—
—
—
30
15
—
8
8
Unit
fbus
tbus
tsck
tsck
tsck
ns
ns
ns
ns
ns
ns
ns
134
For More Information On This Product,
Go to: www.freescale.com
Share Link: 
