Pinout
PTA0
1
PTA1
2
PTA2
3
PTA3
4
ADC0_DP1/ADC0_SE2
5
ADC0_DM1/ADC0_SE3
6
VDDA
7
VSSA
8
24
VDD
23
EXTAL2
22
XTAL2
21
BKGD/MS
20
ADC0_SE18/TSI0_CH14
19
ADC0_SE17/TSI0_CH13
18
TSI0_CH10
17
IRQ/EZP_MS_b
Figure 25. 32-pin QFN
8.3 Module-by-module signals
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
64-pin
1
24
Table 35. Module signals by GPIO port and pin
48-pin
44-pin
32-pin
Power and ground
Port
20
18
Table continues on the next page...
Module signal(s)
VDD
VDD
MCF51QH128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
57