MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
Table 4-4. Cache Tag Data Format (for Test Mode Read/Write Operation)
Bits
31
30:23
22
21
20:0
Cache Tag Data Format
Description
LRU bit, accessible only through Way 0 Tag Read
Unused Bits
Lock
Valid
A[31:11]
4.2.1.3 Cache RAM
The Cache RAM consists of four 512 X 16 Asynchronous Static RAM modules, and they are organized into two
512 words (32 bit/word) to support two way set associative. The memory map for direct accesses while in Test
Mode or Lock Mode is as follows:
WAY 0: $01FE0000-$01FE07FF
WAY 1: $01FE0800-$01FE0FFF
4.2.1.4 Cache Tags
The Cache Tags are defined as follows:
Valid (1 bit):
A 1 in this bit indicates that the Tags and data at the addressed Cache Line are both valid.
Neither Tags nor data have meaning if this bit is 0. Upon power up, the tag memories will
undergo an automatic flush operation that requires 128 clocks. During the flush operation, the
cache is disabled.
Lock (1 bit): A 1 in this bit indicates that the Tags and data at the addressed Cache Line are both valid and
locked and should not be replaced when a Cache miss is detected.
LRU (1 bit):
Indicates that the Tags and data at the addressed Cache line (if not locked) at Way 0 can be
replaced if this bit is 0. If this bit is a 1, the Cache Line and Tags in Way 1 should be chosen for
replacement.
Unused (8 bits): Unused bits are undefined.
A[31:11]:
Address Tag bits which together with Cache address (A[10:4]), uniquely identify a Cache Line in
the entire 32-bit physical address space.
The Cache Tags are memory mapped to the following address space (not fully utilized) when in the Test Mode or
Lock Mode :
WAY 0: $01FE1000-$01FE17FF
WAY 1: $01FE1800-$01FE1FFF
It should be noted that bits 2-3 of the addresses are not decoded during the Tag entry accesses, i.e., $sa+00,
$sa+04, $sa+08, and $sa+0C all access the same Tag entry.
4.2.1.5 Accessing the Cache
To access the Cache during an instruction fetch, the Cache Controller performs the normal cache operation. If
accesses are performed during Test mode or Lock mode, the Tag RAM and Cache RAM are treated as regular
memories.
If the Cache is enabled, regardless of cache hit or miss, the Cache Controller asserts one wait state for every
non-sequential cycle to start the instruction fetch cycle.
4-20
Conexant
100723A
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