MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
If the access results in a hit, the wait state is de-asserted and a 32-bit Cache data is output to the ARM.
Subsequent Sequential (S-cycles) access(es) require zero wait state if they are found in the same Cache Line. If
the access crosses Cache Line boundary, the Cache Controller will add one wait state for the first S cycle that
crosses the boundary, and then add additional wait states if it results in a cache miss.
If the access misses the Cache, the Cache Controller extends the wait states until the corresponding cache data
or cache line is received from external memory through SIU. The number of wait states inserted is affected by the
status of the lock bit for the corresponding Cache Line. If the Line is not locked, then the Cache Line fill operation
will be performed and the required wait state will depend on the speed and the data width of the external devices.
If the Cache Line is locked, the Cache Controller will re-generate the ARM cycle and forward the cycle to SIU.
The required wait states in this case will be much less than that of Cache Line fill, but still a few cycles more than
a simple pass-through operation when the Cache is disabled. This is due to the time required for the tag
comparison. It should be noted that, in the case of Cache Line fill, the requested data is not transferred to the
ARM until the Cache Line fill operation is completed.
4.2.1.6 Definition of a Cache Hit
There are two requirements for a Cache hit. First the ARM A[31:11] must match the Cache Address Tags
accessed by A[10 :4] in an instruction fetch cycle. Second, the addressed Cache Line must be Valid.
4.2.1.7 LRU Algorithm
The LRU (Least Recently Used) algorithm is applied when a Cache miss is detected. This algorithm first looks for
a non-valid Line in the Set for a replacement. The order that is used for this checking is Way 0 first, then Way 1. If
both lines associated with the Set are valid, then the Lock bit check is followed. If both are not locked, then the
LRU bit (one bit only) associated with the Set is tested. If it is a zero, the Cache Line in Way 0 is replaced;
otherwise, Way 1. If both are locked, no replacement can be performed and the Cache Controller will convert the
cycle from instruction fetch to data fetch and forward the cycle to SIU for the requested instruction. If only one of
the two lines is locked, the unlocked line will be chosen for the replacement.
4.2.1.8 SIU interface
The ARM to SIU interface behaves differently depending on whether the Cache is enabled or not. If the Cache is
disabled, the only affect that the Cache Controller adds to the ARM/SIU interface is a small propagation delay for
those signals that pass through the Cache Controller (refer to the block diagram for the pass-through signals). On
the other hand, if the Cache is enabled, the Cache controller will response to an instruction cycle by either
providing data to the ARM in a cache hit, or, converting the instruction cycle to a series of burst data cycle(s) and
forwarding them to SIU in a cache miss.
100723A
Conexant
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