MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
Table 4-5. Access Modes for Reading ROM
ROM Access
Mode
8-bit non-
interleave
Data Type
instruction
Cache Memory
Cache enabled
and Cache miss
16-bit non-
interleave
8-bit non-
interleave
16-bit non-
interleave
8-bit non-
interleave
16-bit non-
interleave
16-bit 2-way
interleave
instruction Cache enabled
and Cache miss
instruction Cache disabled
instruction Cache disabled
data
Not applied
data
Not applied
instruction Cache enabled
and Cache miss
16-bit 2-way
interleave
instruction Cache disabled
16-bit 2-way data
interleave
Cache enabled
and Cache miss
Wait States
Notes
w,w,w,w,w,w,w,w
w,w,w,w,w,w,w,w
(16 sequential accesses)
w,w,w,w,w,w,w,w
(8 sequential accesses)
w
w
w
w
w, s,
w-s-1, s,
w-s-1, s,
w-s-1, s
(8 sequential accesses)
w, s,
w-s-1, s,
w-s-1, s,
w-s-1, s
(one interleave access
sequence)
The actual sequential
access length is dynamic.
w, s,
w-s-1, s,
w-s-1, s,
w-s-1, s
(one interleave access
sequence)
The actual sequential
access length is dynamic.
This is cache burst access. Save the address decoding
cycle for all accesses except the first access.
This is cache burst access. Save the address decoding
cycle for all accesses except the first access.
If the sequential access occurs, save the address decoding
cycle for all accesses except the first access.
If the sequential access occurs, save the address decoding
cycle for all accesses except the first access.
If the sequential access occurs, save the address decoding
cycle for all accesses except the first access.
If the sequential access occurs, save the address decoding
cycle for all accesses except the first access.
This is cache burst access. 0 or 1 wait state is
programmable and depends on the CPU clock frequency
and the ROM speed. If ‘w-s-1’ is less than 1, it will be forced
to 1.
0 or 1 wait state is programmable and depends on the CPU
clock frequency and the ROM speed. If the starting address
of the sequential access is not lined up with the octal
address boundary of the interleave access, the partial
interleave access sequence should be done. Then, restart
the interleave access sequence at the octal address
boundary of the interleave access. Even if the stopping
address of the sequential access is not lined up with the
octal address boundary of the interleave access, the access
sequence must be stopped immediately at anywhere. If ‘w-
s-1’ is less than s, it will be forced to s.
0 or 1 wait state is programmable and depends on the CPU
clock frequency and the ROM speed. If the starting address
of the sequential access is not lined up with the octal
address boundary of the interleave access, the partial
interleave access sequence should be done. Then, restart
the interleave access sequence at the octal address
boundary of the interleave access. Even if the stopping
address of the sequential access is not lined up with the
address boundary of the interleave access, the access
sequence must be stopped immediately at anywhere. If ‘w-
s-1’ is less than s, it will be forced to s.
100723A
Conexant
4-27
Share Link: 
