MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
If the ROM write access (Flash memory in the ROM address range) is performed in the interleave access mode,
the SIU still generates those signals to control ROMs and external multiplexes to perform the interleave access.
But, all the access (no matter if it is the sequential access or not) have W wait states.
External DRAM Interface
When the decoded address from any bus master matches external DRAM address, the SIU will issue a DRAM
request to the DRAM controller and start the transaction . First, it routes the DRAM row address to the address
bus. After receiving the column enable signal from the DRAM controller, the SIU multiplexes the DRAM column
address to the same address bus according to the size of the DRAM . The SIU will perform the next transaction
after receiving the DRAM ready back from the DRAM controller signaling the DRAM transaction is complete.
The SIU also looks at the burst request signals from the bus master who owns the bus to generate the BURST
signal to the DRAM Controller indicating a burst access.
Bus Arbitration
The bus arbitrator block arbitrates control of the internal and external busses between the ARM7TDMI core and
any bus master devices (such as DMA) residing on the IPB or ISB. The ARM core is the default bus master and
has control of the bus whenever no other bus master requests it . In arbitrating control of the bus, the arbitrator
gives highest priority to the DMA Controller and then, the ARM core.
In burst mode access (both DMA and CPU), the bus is not arbitrated within the burst access. In order to prevent a
bus master from hogging the bus. The maximum burst length allowed is eight halfword access. The DMA of
internal peripherals only bursts a maximum of five halfwords.
A bus master requests the bus by asserting request. The arbitrator grants the bus to the requesting bus master by
asserting grant. The requesting bus master must continue to assert request for as long a bus ownership is
required and release the bus by de-asserting request. The arbitrator always inserts a single dead cycle before
granting the bus to another bus master.
Little Endian and Big Endian
The little endian and big endian control is only for internal DMA (The DMA request is from an internal peripheral).
When a DMA access requires different endian format. the corresponding bit of the DMAEndian register needs to
be set. The SIU will transform the endian format; from little endian DMA address and data into big endian format
or from big endian DMA address and data into little endian format. The even and odd write signals (WREn,
WROn) also change accordingly. The following tables show the final addresses and data at the ASIC pins, and
the resulting DMA read or write data. Internal DMA data size is always 16 bits (a halfword).
4-28
Conexant
100723A
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