MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
4.2.3 Firmware Operation
4.2.3.1 Enabling the Cache
The Cache Enable bit in the SIU Cache Control register determines if the Cache is enabled or not. In power-up
reset state, the Cache is disabled. If disabled, all CPU accesses go directly to the SIU and the Cache Controller
passes through all signals from ARM to SIU. After the power-up reset, all Cache Tag entries are flushed after 128
clocks. If the Cache is enabled after power-up, the Cache Controller starts to update the Cache memory and
Cache tag after the flush operation is completed.
4.2.3.2 Locking the Cache
The system can lock the entire cache memory by setting GLOBAL LOCK bit to 1 in Cache Control register. The
Cache remains locked until the bit is reset. Setting and resetting the Global _Lock bit has no effect on the
individual lock bit set during the Lock mode, the individual lock bit can be cleared by setting Flush_Cache bit to 1.
The system can also lock an individual Cache Line by placing the Cache in the Lock Mode. Once in the Lock
mode, the system can access the Cache RAM and Tag RAM as if they were regular memory. A write to the Tag
entry sets both the Lock bit and Valid bit for the corresponding Tag. The software is responsible for properly
mapping the instructions from ROM (‘where to be cached in’) into Cache RAM and Tag RAM (‘where to be locked
down’) based on the modular of 2048 bytes. In other words, the A10-A2 of address lines used for the ROM code
and Cache/Tag RAM’s entry must be identical, and the A31-A11used for the ROM code becomes the data entry
for the corresponding Tag entry. Caching is disabled during lock mode; the system must exit the lock mode before
enabling the Cache.
Once a Cache line is locked, LRU replacement policy prevents the replacement of the locked Cache Line. If both
Cache Lines in a Set (two Ways) are locked, the LRU algorithm is not able to replace either Line; thus, no Cache
Line fill is performed; instead, a data fetch N (non-sequential) cycle is generated by the Cache Controller and sent
to the SIU. A minimum of 5 wait states is expected.
4.2.3.3 Flushing the Cache
The system can clear the Cache by activating the Flush input. This signal is generated by the SIU when the Flush
bit in the Cache Control register is set by the system. Upon receiving the Flush input, the Cache Controller starts
the flush operation. The operation takes 128 clocks to resets all the Tag Valid bits, LRU bit, and Lock bit. During
the operation the cache, if enabled, is temporarily disabled until the flush is completed. The Flush bit is cleared
automatically at the end of the flush operation.
4.2.3.4 Testing the Cache and Tag Memories
The system can access the Cache memory and Tag RAM as regular memory does when in Test mode. Test
mode is entered after setting the Test bit in the Cache Control register. In Test mode, the Tag RAM and Cache
RAM behave like an ordinary memory for read/write cycles. This test feature is not only required for the power-up
self test, but also is important for diagnostics when a system problem develops. The contents of the TAG and
Cache RAM are essential to the investigation of the problem.
Note: The Valid bit, Lock bit, and LRU bit can only be read, not written, and LRU is only
available through Way 0 access.
Note: It is important to flush the Cache upon completion of the Test Mode.
100723A
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