MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
ISB Bus
The ISB Bus is used for connecting ARM and Cache Controller to the highest performance. The 32-bit ISB bus
directly interfaces with the ARM core 32-bit data bus. The cache memory controller resides on this bus.
All control signals to and from the ARM, and its address bus go through the cache memory controller regardless
of the cache enable bit. The cache controller control register resides in the SIU.
When the ARM is fetching instructions, and it is a cache hit situation, the ARM gets the instructions from the
cache. The SIU lets the other bus masters have the bus.
When the ARM is fetching instructions, and it is a cache miss situation, the SIU must perform a burst read of eight
halfwords (4 words) to fill up the cache line if the cache line is not locked. If the cache line is locked, then the SIU
reads in two halfwords (one word) of instruction.
When the ARM is fetching data, data is passed directly from the SIU to the ARM.
EB Bus
The EB Bus is used for connecting external memories and devices. The width of the selected slave device is
programmable in the chip select configuration register. The external A[23:12] and A[11:0] addresses are
multiplexed through A[11:0] pins. The ALE signal is provided to latch A[23:12] addresses externally.
External Chip Selects
The SIU provides programmable external chip selects. Each chip select is programmable through the chip select
configuration register.
• Each chip select can be configured to be:
• enabled or disabled (default = enabled).
• programmable from 0 up to 7 wait states.
• programmable read/write delay-on (write strobe activated one or two SIUCLK cycles later).
• programmable write early-off (read or write strobe deactivated one SIUCLK cycle earlier).
• programmable to allow for 8 or 16 bit devices. The SIU will automatically perform the necessary transaction to
access any size data as long as the source of the transaction is internal.
Note: The RD/WR-delay-on and WR-early-off settings should be disabled for zero wait state
access. For other wait state settings (> 1wait state), the delay-on and early-off will shorten the
width of read/write strobe. Firmware has the responsibility to set RD/WR-delay-on and WR-
early-off bits correctly. Otherwise, read or write strobes may disappear. For example, if 1 wait
state and 1 RD/WR-delay-on are set for a chip select, the read strobe is not suppressed when
firmware tries to do a read operation. If 2 wait states, 1 WR-early-off and 1 RD/WR-delay-on are
set for a chip select, the write strobe is not suppressed when firmware try to do a write operation.
ROM Interface
The SIU supports non-interleave, 2-way interleave and fast page mode access to ROM, depending on the ROM
Access Configuration pins (AE[2]/ROM_CFG[0] and AO[2]/ROM_CFG[1] pins). Following are the four
configurations supported by the SIU.
ROM Access Configuration[1:0]
00
01
10
11
ROM Mode
8-bit non-interleave
16-bit non-interleave
16-bit 2-way interleave
16-bit fast page mode
100723A
Conexant
4-25
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