MK68564 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'MK68564' PDF : 46 Pages View PDF
MK68564
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5.0 VDC ± 5%, GND = 0 VDC, TA = 0 to 70°C)
Number
Parameter
40 CS HIGH TO DATA Out High Impedence
41 CS or IACK High to CLK Low
42 TxRDY or RxRDY Width Low
43 CLK High TxRDY or RxRDY Low
44 CLK High to TxRDY or RxRDY High
IACK High to CS Low or CS High to IACK Low
(not shown)
4.0 MHz
Min. Max.
120
100
3
300
300
50
5.0 MHz
Min. Max.
90
100
3
300
300
50
Unit
ns
ns
CLK’s
ns
ns
ns
Notes
7
8, 10
1
45 CTS, DCD, SYNC Pulse Width High
46 CTS, DCD, SYNC Pulse Width Low
47 TxC Period
48 TxC Width Low
49 TxC Width High
50 TxC Low to TxD Delay (X1 Mode)
51 TxC Low to INTR Low Delay
200
200
ns
200
200
ns
1000 DC
800
DC
ns
9
180
DC
180
DC
ns
180
DC
180
DC
ns
300
300
ns
5
9
5
9
CLK’s
10
52 RxC Period
1000
DC
800
DC
ns
9
53 RxC Width Low
180
DC
180
DC
ns
54 RxC Width High
180
DC
180
DC
ns
55 RxD to RxC High Setup Time (X1 mode)
0
0
ns
56 RxC High to RxD Hold Time (X1 mode)
140
140
ns
57 RxC High to INTR Low Delay
10
13
10
13 CLK’s 10
58
RxC High to SYNC Low Delay (output modes)
4
7
4
7
CLK’s 10
59 RESET Low
1
1
CLK
10
60 XTAL 1 Width High (TTL in)
61 XTAL 1 Width Low (TTL in)
62 XTAL 1 Period (TTL in)
63 XTAL 1 Period (crystal in)
100
80
ns
100
80
ns
250 2000 200 2000
ns
250 1000 200 1000
ns
Not es : 1. This specification only applies if the SIO has completed all operations initiated by the previous bus cycle, when CS
or IACK was asserted. Following a read, write, or interrupt acknoledge cycle, all operations are complete within two
CLK cycles after the rising edge of CS or IACK. If CS or IACK is asserted prior to the completion of the internal
operations, the new bus cycle will be postponed.
2. If IEI meets the setup time to the falling edge of CLK, 1 1/2 cycles following the clocking in of IACK.
3. No internal interrupt request pending at the start of an interrupt acknoledge cycle.
4. Time starts when first signal goes invalid (high).
5. If an internal interrupt is pending at the end of the interrupt acknoledge cycle.
6. If Note 2 timing is not met.
7. If this spec is met, the delay listed in Note 1 will be one CLK cycle instead of two.
8. Ready signals will be negated asynchronous to the CLK, if the condition causing the assertion of the signals is
cleared.
9. If RxC and TxC are asynchronous to the System Clock, the maximum clock rate into RxC and TxC should be no
more than one-fifth the System Clock rate. If RxC and TxC are synchronized to the falling edge of the System
Clock, the maximum clock rate into RxC and TxC can be one-fourth the System Clock rate.
10. System Clock.
11. Due to the dynamic nature of the internal data bus, if CS is held low for more than a few hundred milli seconds the
38/46
Share Link: 
