ML2713CH View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2713CH' PDF : 18 Pages View PDF
PRELIMINARY
OPERATIONAL MODES (CONTINUED)
RECEIVER CIRCUITS
DC Restoration
ML2713
The main circuits active in the receive mode are:
Image Reject Receive Mixer
The image reject receive mixer consists of an input
splitter, a 2LO input buffer, a 0/90 degree splitter, two
mixers and a 0/90 degree IF combiner. The 0/90 degree
networks are passive and internal to the IC. The design of
the mixer is centered to give optimum performance with
a 260MHz 1IF, 24MHz 2IF. Under these conditions the
image rejection is typically better than 25dB.
The differential 2LO input port has a nominal 200W
impedance. The 2LO port is a low impedance common
base stage such that the 2LO signal is not attenuated by
the parasitic capacitance of the ML2712, ML2713, the
interconnect between them, and their packages. Each
input requires external pull down resistors of 4k to
properly bias them. These resistors are internal to the
ML2712, and do not need to be included if that device is
used.
2IF FILTER
The 2IF filter requires two external inductors and four
external capacitors. This circuit is differential to minimize
noise pick up in the 2IF circuit. This filter is auto aligned
and is slaved to the discriminator. The ML2713 has been
designed so that the same inductors and nearly the same
capacitors can be used in both the discriminator and filter.
It is recommended that the same inductors be used for the
two circuits and that they be co-located on a reel of
components. This will ensure minimal difference between
the inductor values so that the filter and discriminator
center frequencies are very similar, if not identical.
Discriminator Phase Shift
The discriminator performs the frequency to voltage
conversion. The 0/90 degree phase shift is internal, but
external components (one inductor and one capacitor) are
required for the differential phase shift versus frequency
(d/df). The center frequency of the d/df circuit is tuned by
a capacitor array during Align Mode. This capacitor array
has a nominal variation of 10pF, which for a 24MHz IF is
sufficient to cope with a 10% total component tolerance
(including temperature) in the external L and C (e.g., 5%
capacitor & 5% inductor tolerance).
Receiver Data Filter
The receiver is intended for use in TDMA radios. This
requires rapid turn on of circuits, then the ability to
remove the effect of DC offsets and the frequency offset
of any received signal.
DC restoration circuits on the ML2713 let the acquisition
time be controlled by the value of an external capacitor.
The DC restoration, during acquisition, forces the mean
input voltage of the comparator to equal the mid-range
voltage of the D/A. This is important as it minimizes the
number of bits required in the tracking A/D. This DC
restoration is achieved by estimating the mean level of
the receive data filter output voltage and subtracting the
difference between this and the D/A mid point. For small
errors a single pole internal resistor and external capacitor
is used to calculate the mean. When the error is large
(e.g., when first enabling the receiver or at the start of a
TDMA packet) a fast charge circuit speeds acquisition.
Receive A/D
External digital circuits can be used to make a tracking
A/D converter by using the D/A and comparator. The
digital circuits try to force the A/D output to be the same
as the received signal input to the comparator. The digital
circuits require an up/down counter, which will drive the
D/A. This is shown in Figure 6.
+
–
6 BIT D/A
CMO
DD0 - DD5
COUNT
UP/DOWN
TO DEMODULATOR
Figure 6. Tracking ADC Block Diagram
When the receive signal at the comparator input voltage
is greater than the D/A output voltage (inverting input to
comparator), the comparator output (CMO) goes high,
which increments the digital counter, which in turn
increases the D/A output voltage. The circuit is clocked to
keep the D/A output tracking the received signal. If the
comparator output is low, then the counter decrements
and reduces the D/A output voltage. This means the
output of the D/A, or the counter output, is a digitized
version of the received signal. This is shown in Figure 7.
V
RECEIVED SIGNAL
D/A OUTPUT
The receiver data filter is made up of two on chip unity
gain op-amps, and off chip inductors and resistors
configured as a 5th order filter. This filter does not need to
be tuned or aligned.
CMO
SAMPLE
CLOCK
IN
COUNTER
TIME
Figure 7. Receive Tracking A/D Signals Illustrated
January, 2000 PRELIMINARY DATASHEET
13
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