ML2713CH View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2713CH' PDF : 18 Pages View PDF
PRELIMINARY
ML2713
OPERATIONAL MODES (CONTINUED)
The D/A voltage (overlaid on the received signal) and the
CMO output are relative to the sample clock of the
external counter circuit. For some applications the counts
and D/A output can be incremented and decremented in
one LSB. However, if the rate of change of voltage is too
high, then two or more counts/LSB may needed to keep
track of the received signal. A typical application is
where the update rate of the tracking A/D is 16MHz.
SLEEP MODE
When going into sleep mode all circuits are powered off
and the chip typically draws less than 1mA. Sleep mode
also resets the alignment up/down counter to its
midpoint.
Test Mode Control
RSSI
The Received Signal Strength Indicator (RSSI) is generated
by summing the signal measured in the 2IF limiter and
the 1IF amplifier. Inclusion of the 1IF amplifier in the
RSSI equation enables the maximum input level to be
higher than with normal IF superheterodyne receiver ICs.
The RSSI output is referenced to VCC2 and decreases with
increasing signal level. See Figure 8. The RSSI output is
compatible with the ML2712's RSSI A/D converter. The
rise and fall times are typically 4msec which is ideal for
performing clear channel assessment or preamble antenna
diversity in a WLAN system.
MS1, MS2, and MS3 are CMOS logic inputs that activate
on chip test modes. For normal operation, ground all of
these pins. Each of these pins has a large value pull
down resistor to ground. Tying MS1 to VCC4 will disable
the Filter Align circuitry. Tying MS2 to VCC2 will disable
the Receive A/D converter by shutting off both the 6-bit
D/A converter and comparator in the receive mode. MS3
should remain tied to ground at all times.
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
–100 –80 –60 –40 –20 0
20
POWER (dBm)
Figure 8. Typical RSSI Response with a 260MHz 1IF
14
PRELIMINARY DATASHEET January, 2000
Share Link: 
