ML2724 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2724' PDF : 26 Pages View PDF
ML2724
STANDBY MODE
In STANDBY mode, the ML2724 transceiver is powered down. The only circuits active are the control interfaces, which
are digital CMOS to minimize power consumption. The serial control interface and control registers remain powered up
and will accept and retain programming data as long as the digital supply is present. When exiting STANDBY mode, the
device may need to be kept in RECEIVE mode for up to 256μs to allow for filter self-calibration.
TEST MODE
The RF to digital functionality of the ML2724 requires special test mode circuitry for IC production test and radio
debugging. A test register, accessible via the 3-wire serial interface, controls the test multiplexers. (See Table 15).
DATA INTERFACE
There are two control interfaces: CONTROL and SERIAL.
CONTROL INTERFACE
The control interface provides immediate control and monitoring of the ML2724. Input signals include:
XCEN:
Transceiver enable. Places the ML2724 in Standby or Active (when asserted) modes.
RXON:
Receive On. Places an Active ML2724 in Receive mode when asserted.
FREF:
Reference frequency input
Output signals include:
RSSI:
Received Signal Strength Indicator: indicates the power of the received signal
PAON:
External Power Amplifier Control Pin
SERIAL INTERFACE
A 3-wire serial interface (EN, DATA, CLK) is used for programming the ML2724 configuration registers, which control
device mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are
entered beginning with the MSB (“big-endian”). The word is divided into a leading 14-bit data field followed by a 2-bit
address field. When the address field has been decoded the destination register is loaded on the rising edge of EN.
Providing less than 16 bits of data will result in unpredictable behavior when EN goes high.
Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift
register on the rising edge of the CLK pin. This information is loaded into the target control register when EN goes high.
This serial interface bus is similar to that commonly found on PLL devices. It can be efficiently programmed by either
byte or 16-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal power
when the bus is inactive. Refer to Figure 4 and Table 2: 3-Wire Bus Timing Characteristics for timing and register
programming illustrations.
DS2724-F-03
SYMBOL PARAMETER
BUS CLOCK (CLK)
tr
CLK input rise time
tf
CLK input fall time
tck
CLK period
ENABLE (EN)
tew
Minimum pulse width
tl
Delay from last CLK rising edge
tse
Set up time to ignore next rising CLK
MIN TYP MAX UNIT
15
ns
15
ns
50
ns
100
ns
15
ns
15
ns
FINAL DATASHEET
DECEMBER 2005 15
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