ML2724DH-T View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2724DH-T' PDF : 26 Pages View PDF
ML2724
CONTROL INTERFACES AND REGISTER DESCRIPTIONS
REGISTER INFORMATION
A 3-wire serial data input bus sets the ML2724’s transceiver parameters and programs the PLL circuits. Entering 16-bit
words into the ML2724 serial interface performs programming. Three 16-bit registers are partitioned such that 14 bits
are dedicated for data to program the operation and two bits identify the register address. The contents of these
registers cannot be read back via this bus.
The three registers are:
Register 0:
PLL Configuration
Register 1:
Channel Frequency Data
Register 2:
Internal Test Access
Figure 5 shows a register map. Table 3 through Table 5 provide detailed diagrams of the register organization: Table 3
and Table 4 outline the PLL configuration and channel frequency registers, and Table 5 displays the filter tuning and
test mode register.
MSB
DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADR1 ADR0
Res.
Res. Res. Res. RCLP LVLO Res.
TXM
TPC TXCW Res. AOUT RD0
QPP
0
0
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MSB
DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADR1
Res.
Res. CHQ11 CHQ10 CHQ9 CHQ8 CHQ7 CHQ6 CHQ5 CHQ4 CHQ3 CHQ2 CHQ1 CHQ0
0
ADR0
1
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MSB
DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADR1 ADR0
Res.
Res. Res. Res.
Res.
Res. Res.
Res. DTM2 DTM1 DTM0 ATM2 ATM1 ATM0
1
0
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 5: Configuration Register Map
DS2724-F-03
FINAL DATASHEET
DECEMBER 2005 17
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