ML9042 View Datasheet(PDF) - LAPIS Semiconductor Co., Ltd.
Part Name
Description
MFG CO.
'ML9042' PDF : 58 Pages View PDF
LAPIS Semiconductor
FEDL9042-01
ML9042-xx
Instruction Codes
Table of Instruction Codes
Instruction
Code
RS1
RS0/
CSB
RW/
SI
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
(SO)
Function
Execution
Time
f = 270 kHz
Display Clear
Clears all the displayed digits of the
10
0
0000
0
0
0
1
LCD and sets the DDRAM address 00
in the address counter. The arbitrator
1.52 ms
data is cleared.
Cursor Home
Sets the DDRAM address 00 in the
1
0
0
0
000
0
0
1
X
address counter and shifts the display
back to the original. The content of the
1.52 ms
DDRAM remains unchanged.
Entry Mode
Setting
Determines the direction of movement
1
0
0
0
0
0
0
0
1
I/D
S
of the cursor and whether or not to shift
the display. This instruction is
37 s
executed when data is written or read.
Display
ON/OFF Control
1
0
0
0
000
1
DC
Sets LCD display ON/OFF (D), cursor
B ON/OFF (C) or cursor-position
character blinking ON/OFF (B).
37 s
Cursor/Display
Shift
1
0
Moves the cursor or shifts the display
0 0 0 0 1 S/C R/L X X without changing the content of the
DDRAM.
37 s
Sets the interface data length (DL), the
number of display lines (N), the
Function Setting 1 0 0 0 0 1 DL N ABE SSR CSR arbitrator display (ABE), the segment 37 s
data shift direction (SSR), or the
common data shift direction (CSR).
CGRAM
Address Setting
1
0
0
0
1
ACG
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.
37 s
DDRAM
Address Setting
1
0
0
1
ADD
Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.
37 s
Busy Flag/
Address Read
1
0
1 BF
ADC
Reads the Busy Flag (indicating that
the ML9042 is operating) and the
0 s
content of the address counter.
RAM Data Write 1 1 0
WRITE DATA
Writes data in DDRAM, ABRAM or
CGRAM.
37 s
RAM Data Read 1 1 1
READ DATA
Reads data from DDRAM, ABRAM or
CGRAM.
37 s
Arbitrator
Display Line Set
0
0
0
0
0
0
0
0
0
1 AS Sets the arbitrator display line.
37 s
ABRAM
Address Setting
0
0
0
0
11
AAB
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
37 s
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